The escalating demands for high density and performance associated with non-volatile memory devices require small design features, high reliability and increased manufacturing throughput. The reduction of design features, however, challenges the limitations of conventional methodology. For example, the reduction of design features makes it difficult for the memory device to meet its expected data retention requirement.
One type of conventional electrically erasable programmable read only memory (EEPROM) device includes a silicon substrate with an oxide-nitride-oxide (ONO) stack formed on the substrate. A silicon control gate is formed over the ONO stack. This type of memory device is often referred to as a SONOS (silicon-oxide-nitride-oxide-silicon) type memory device. In a SONOS device, the nitride layer acts as the charge storage layer. In an alternative EEPROM design, the charge storage layer may include a polysilicon floating gate. In a more specific implementation, EEPROM memory devices of these types may be implemented as an array of memory cells configured in a NAND arrangement.